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EP2C35F672I8

Cyclone® II Field Programmable Gate Array (FPGA) IC 475 483840 33216 672-BGA

Manufacturer:

Intel
Mfr.Part #:

EP2C35F672I8
Datasheet:

EP2C35F672I8 Datasheet (PDF)
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Additional Feature:

ALSO REQUIRES 3.3 SUPPLY
EDA/CAD Models:

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EP2C35F672I8 General Description

Cyclone® II Field Programmable Gate Array (FPGA) IC 475 483840 33216 672-BGA

Key Features

High-density architecture with 4,608 to 68,416 LEs
M4K embedded memory blocks
Up to 1.1 Mbits of RAM available without reducing available logic
4,096 memory bits per block (4,608 bits per block including 512 parity bits)
Variable port configurations of ×1, ×2, ×4, ×8, ×9, ×16, ×18, ×32, and ×36
True dual-port (one read and one write, two reads, or two writes) operation for ×1, ×2, ×4, ×8, ×9, ×16, and ×18 modes
Byte enables for data input masking during writes
Up to 260-MHz operation
Embedded multipliers
Up to 150 18- × 18-bit multipliers are each configurable as two independent 9- × 9-bit multipliers with up to 250-MHz performance
Optional input and output registers
Advanced I/O support
High-speed differential I/O standard support, including LVDS, RSDS, mini-LVDS, LVPECL, differential HSTL, and differential SSTL
Single-ended I/O standard support, including 2.5-V and 1.8-V, SSTL class I and II, 1.8-V and 1.5-V HSTL class I and II, 3.3-V PCI and PCI-X 1.0, 3.3-, 2.5-, 1.8-, and 1.5-V LVCMOS, and 3.3-, 2.5-, and 1.8-V LVTTL
Peripheral Component Interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification, Revision 3.0 compliance for 3.3-V operation at 33 or 66 MHz for 32- or 64-bit interfaces
PCI Express with an external TI PHY and an Altera PCI Express ×1 Megacore® function
133-MHz PCI-X 1.0 specification compatibility
High-speed external memory support, including DDR, DDR2, and SDR SDRAM, and QDRII SRAM supported by drop in Altera IP MegaCore functions for ease of use
Three dedicated registers per I/O element (IOE): one input register, one output register, and one output-enable register
Programmable bus-hold feature
Programmable output drive strength feature
Programmable delays from the pin to the IOE or logic array
I/O bank grouping for unique VCCIO and/or VREF bank settings
MultiVolt™ I/O standard support for 1.5-, 1.8-, 2.5-, and 3.3-interfaces
Hot-socketing operation support
Tri-state with weak pull-up on I/O pins before and during configuration
Programmable open-drain outputs
Series on-chip termination support
(Continue .)

Specifications

Part Life Cycle Code	Active	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Additional Feature	ALSO REQUIRES 3.3 SUPPLY
Clock Frequency-Max	402.5 MHz	JESD-30 Code	S-PBGA-B672
JESD-609 Code	e0	Length	27 mm
Moisture Sensitivity Level	3	Number of CLBs	2076
Number of Inputs	475	Number of Logic Cells	33216
Number of Outputs	459	Number of Terminals	672
Organization	2076 CLBS	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	2.6 mm
Supply Voltage-Max	1.25 V	Supply Voltage-Min	1.15 V
Supply Voltage-Nom	1.2 V	Surface Mount	YES
Technology	CMOS	Terminal Finish	TIN LEAD
Terminal Form	BALL	Terminal Pitch	1 mm
Terminal Position	BOTTOM	Width	27 mm