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AGLN010V2-QNG48

FPGA - Field Programmable Gate Array AGLN010V2-QNG48

email Email: [email protected]
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AGLN010V2-QNG48 General Description

IGLOO nano Field Programmable Gate Array (FPGA) IC 34 260 48-VFQFN Exposed Pad

Specifications

Part Life Cycle Code Active Reach Compliance Code compliant
HTS Code 8542.39.00.01 JESD-30 Code S-XQCC-N48
JESD-609 Code e3 Length 6 mm
Moisture Sensitivity Level 3 Number of CLBs 260
Number of Equivalent Gates 10000 Number of Terminals 48
Operating Temperature-Max 70 °C Operating Temperature-Min -20 °C
Organization 260 CLBS, 10000 GATES Peak Reflow Temperature (Cel) 260
Programmable Logic Type FIELD PROGRAMMABLE GATE ARRAY Qualification Status Not Qualified
Seated Height-Max 1 mm Supply Voltage-Max 1.575 V
Supply Voltage-Min 1.14 V Supply Voltage-Nom 1.2 V
Surface Mount YES Technology CMOS
Temperature Grade OTHER Terminal Finish MATTE TIN
Terminal Form NO LEAD Terminal Pitch 0.4 mm
Terminal Position QUAD Time@Peak Reflow Temperature-Max (s) 30
Width 6 mm

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