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See Technical Specifications

TMS320C6211BGFN150 +BOM

C62x fixed point DSP- up to 167MHz

Manufacturer:

Texas Instruments, Inc
Mfr.Part #:

TMS320C6211BGFN150
Datasheet:

TMS320C6211BGFN150 Datasheet (PDF)
Series:

TMS320C62x
Type:

Fixed Point
Interface:

Host Interface, McBSP
Clock Rate:

150MHz
EDA/CAD Models:

Request Free CAD Models for TMS320C6211BGFN150

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TMS320C6211BGFN150 General Description

The TMS320C6211BGFN150 is a high-performance DSP that offers a multitude of features for efficient and cost-effective solutions in various applications. With a clock rate of 167 MHz, this DSP can deliver up to 1333 million instructions per second, making it a powerhouse for demanding tasks. Its VelociTI VLIW architecture allows for a high degree of parallelism with eight functional units, providing six ALUs and two 16-bit multipliers for optimal performance. Additionally, the C6211BGFN150 comes equipped with a two-level cache-based architecture, ensuring quick access to data and instructions, alongside a diverse set of peripherals like McBSPs, timers, and an EMIF for seamless interfacing with external memory

Key Features

Excellent Price/Performance Digital Signal Processors (DSPs): TMS320C62x™ (TMS320C6211 and TMS320C6211B)
- Eight 32-Bit Instructions/Cycle
- C6211, C6211B, C6711, and C6711B are Pin-Compatible
- 150-, 167-MHz Clock Rates
- 6.7-, 6-ns Instruction Cycle Time
- 1200, 1333 MIPS
- Extended Temperature Device (C6211B)
VelociTI™ Advanced Very Long Instruction Word (VLIW) C62x™ DSP Core (C6211/11B)
- Eight Highly Independent Functional Units:
  - Six ALUs (32-/40-Bit)
  - Two 16-Bit Multipliers (32-Bit Results)
- Load-Store Architecture With 32 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
Instruction Set Features
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
L1/L2 Memory Architecture
- 32K-Bit (4K-Byte) L1P Program Cache (Direct Mapped)
- 32K-Bit (4K-Byte) L1D Data Cache (2-Way Set-Associative)
- 512K-Bit (64K-Byte) L2 Unified Mapped RAM/Cache (Flexible Data/Program Allocation)
Device Configuration
- Boot Mode: HPI, 8-, 16-, and 32-Bit ROM Boot
- Endianness: Little Endian, Big Endian
32-Bit External Memory Interface (EMIF)
- Glueless Interface to Asynchronous Memories: SRAM and EPROM
- Glueless Interface to Synchronous Memories: SDRAM and SBSRAM
- 512M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (16 Independent Channels)
16-Bit Host-Port Interface (HPI)
- Access to Entire Memory Map
Two Multichannel Buffered Serial Ports (McBSPs)
- Direct Interface to T1/E1, MVIP, SCSA Framers
- ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral-Interface (SPI) Compatible (Motorola™)
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock Generator
IEEE-1149.1 (JTAG) Boundary-Scan-Compatible
256-Pin Ball Grid Array (BGA) Package (GFN and ZFN Suffixes)
0.18-µm/5-Level Metal Process
- CMOS Technology
3.3-V I/Os, 1.8-V Internal

TMS320C62x, VelociTI, and C62x are trademarks of Texas Instruments.
Motorola is a trademark of Motorola, Inc.
All trademarks are the property of their respective owners.
IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.

Specifications

Category	Integrated Circuits (ICs)EmbeddedDSP (Digital Signal Processors)	Series	TMS320C62x
Type	Fixed Point	Interface	Host Interface, McBSP
Clock Rate	150MHz	Non-Volatile Memory	External
On-Chip RAM	72kB	Voltage - I/O	3.30V
Voltage - Core	1.80V	Operating Temperature	0°C ~ 90°C (TC)
Mounting Type	Surface Mount	Base Product Number	TMS320