This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

SN65LVDS95DGGREP

Enhanced product LVDS SerDes transmitter

Manufacturer:

Texas Instruments, Inc
Mfr.Part #:

SN65LVDS95DGGREP
Datasheet:

SN65LVDS95DGGREP Datasheet (PDF)
Function:

Serializer
Data Rate:

1.3Gbps
Input Type:

LVDS
Output Type:

LVTTL
EDA/CAD Models:

Request Free CAD Models for SN65LVDS95DGGREP

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

SN65LVDS95DGGREP General Description

The SN65LVDS95 LVDS serdes (serializer/deserializer) transmitter contains three 7-bit parallel-load serial-out shift registers, a 7× clock synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These functions allow 21 bits of single-ended LVTTL data to be synchronously transmitted over 4 balanced-pair conductors for receipt by a compatible receiver, such as the SN65LVDS96.

When transmitting, data bits D0 through D20 are each loaded into registers of the SN65LVDS95 on the rising edge of the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to serially unload the data registers in 7-bit slices. The three serial streams and a phase-locked clock (CLKOUT) are then output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.

The SN65LVDS95 requires no external components and little or no control. The data bus appears the same at the input to the transmitter and output of the receiver with data transmission transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN) active-low input to inhibit the clock and shut off the LVDS output drivers for lower power consumption. A low level on this signal clears all internal registers to a low level.

Texas Instruments, IncMicrosoft.AspNetCore.Mvc.Localization.LocalizedHtmlString

Key Features

Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
Enhanced Diminishing Manufacturing
Sources (DMS) Support
Enhanced Product-Change Notification
Qualification Pedigree
21:3 Data Channel Compression at up to
1.36 Gigabits per Second Throughput
Suited for Point-to-Point Subsystem
Communication With Very Low EMI
21 Data Channels Plus Clock in
Low-Voltage TTL and 3 Data Channels Plus
Clock Out Low-Voltage Differential
Operates From a Single 3.3-V Supply and
250 mW (Typ)
5-V Tolerant Data Inputs
’LVDS95 Has Rising Clock Edge Triggered Inputs
Bus Pins Tolerate 6-kV HBM ESD
Packaged in Thin Shrink Small-Outline
Package With 20 Mil Terminal Pitch
Consumes <1 mW When Disabled
Wide Phase-Lock Input Frequency Range
20 MHz to 68 MHz
No External Components Required for PLL
Inputs Meet or Exceed the Requirements of
ANSI EIA/TIA-644 Standard
Industrial Temperature Qualified
T_A = –40°C to 85°C
Replacement for the National DS90CR215

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.

Specifications

Category	Integrated Circuits (ICs)InterfaceSerializers, Deserializers	Series	-
Function	Serializer	Data Rate	1.3Gbps
Input Type	LVDS	Output Type	LVTTL
Number of Inputs	21	Number of Outputs	3
Voltage - Supply	3V ~ 3.6V	Operating Temperature	-40°C ~ 85°C (TA)
Mounting Type	Surface Mount	Base Product Number	65LVDS95
Protocols	HiRel Enhanced Product	Rating	HiRel Enhanced Product
Operating temperature range (°C)	-40 to 85	feature-function	Serializer/Deserializer
feature-number-of-drivers	3	feature-number-of-receivers	21
feature-number-of-elements-per-chip	3	feature-transmission-data-rate-mbps	1360
feature-maximum-propagation-delay-time-ns		feature-input-signal-type	LVTTL
feature-differential-input-low-threshold-voltage-v		feature-differential-input-high-threshold-voltage-v
feature-maximum-differential-output-voltage-v	0.454	feature-maximum-input-current-ua
feature-supplier-temperature-grade	Industrial	feature-packaging	Tape and Reel
feature-rad-hard		feature-pin-count	48
feature-cecc-qualified	No	feature-esd-protection
feature-escc-qualified		feature-military	No
feature-aec-qualified	No	feature-aec-qualified-number
feature-auto-motive	No	feature-p-pap	No
feature-eccn-code	EAR99	feature-svhc	Yes
feature-svhc-exceeds-threshold	No