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See Technical Specifications

PM4354-NGI

Telecom IC, CMOS, PBGA208,

Manufacturer:

Microchip Technology
Mfr.Part #:

PM4354-NGI
Datasheet:

PM4354-NGI Datasheet (PDF)
ECCN (US):

5A991.b
Automotive:

No
PPAP:

No
Number of Transceivers:

4
EDA/CAD Models:

Request Free CAD Models for PM4354-NGI

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

Key Features

Monolithic device which integrates four, full-featured T1 and E1 framers and T1 and E1 short haul and long haul line interfaces.
Software selectable between T1/J1 and E1 operation on a per-device basis.
Meets or exceeds T1 and E1 shorthaul and longhaul network access specifications including ANSI T1.102, T1.403, T1.408, AT&T TR 62411, ITU-T G.703, G.704 as well as ETSI 300-011, CTR-4, CTR- 12 and CTR-13.
Provides encoding and decoding of B8ZS, HDB3 and AMI line codes.
Provides receive equalization, clock recovery and line performance monitoring.
Provides transmit and receive jitter attenuation.
Provides digitally programmable long haul and short haul line build out.
Provides four full-featured HDLC controllers, each with 128-byte transmit and receive FIFO buffers.
Automatically generates and transmits DS-1 performance report messages to ANSI T1.231 and ANSI T1.408 specifications.
Supports Nx64Kbit/s fractional bandwidth backplane.
Supports transfer of PCM data to/from 1.544MHz and 2.048MHz system-side devices. Also supports a fractional T1 or E1 system interface with independent backplane receive/backplane transmit Nx64Kbit/s rates. Supports a 2.048 MHz system-side interface for T1 mode without external clock gapping.
Supports 8.192 Mbit/s, H-100 compatible, H-MVIP on the system interface for all T1 or E1 links, a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CAS channels and a separate 8.192 Mbit/s H-MVIP system interface for all T1 or E1 CCS, V5.1/V5.2, and GR.303 channels.
Provides a selectable, per channel independent de-jittered T1 or E1 recovered clock for system timing and redundancy.
Provides PRBS generators and detectors on each tributary for error testing at DS1, E1 and Nx64Kbit/s rates as recommended in ITU-T O.151 and O.152.
Provides robbed bit signaling extraction and insertion on a per-DS0 basis.
Register level compatibility with the PM4388 TOCTL Octal T1 Framer, the PM6388 EOCTL Octal E1 Framer, the PM4351 COMET E1/T1 transceiver, and the PM8315 TEMUX T1/E1 Framer with integrated Mapper and M13 MUX.
Provides an 8-bit microprocessor bus interface for configuration, control, and status monitoring.
Uses line rate system clock.
Provides an IEEE P1149.1 (JTAG) compliant test access port (TAP) and controller for boundary scan test.
Implemented in a low power 5 V tolerant 2.5/3.3 V CMOS technology.
Available in a high density 208-pin fine pitch PBGA (17 mm by 17 mm) package.
Provides a -40°C to +85°C Industrial temperature operating range.

Specifications

ECCN (US)	5A991.b	Part Status	Obsolete
Automotive	No	PPAP	No
Number of Transceivers	4	Standard Framing Format	E1\|J1\|T1
Mounting	Surface Mount	PCB changed	208
Pin Count	208	Lead Shape	Ball