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OMAP3503DCBC
Processors - Application Specialized App Processor
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Manufacturer: Texas Instruments, Inc
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Mfr.Part #: OMAP3503DCBC
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Datasheet: OMAP3503DCBC Datasheet (PDF)
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Series: OMAP-35xx
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Package: Tray
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Product Status: Obsolete
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Core Processor: ARM® Cortex®-A8
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Availability: 6161 PCS
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OMAP3503DCBC General Description
ARM® Cortex®-A8 Microprocessor IC OMAP-35xx 1 Core, 32-Bit 600MHz 515-POP-FCBGA (14x14)
Key Features
- OMAP3 Devices:
- MPU Subsystem
- NEON SIMD Coprocessor
- Tile-Based Architecture Delivering up to 1 MPoly/sec
- Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
- Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
- Fine-Grained Task Switching, Load Balancing, and Power Management
- Programmable High-Quality Image Anti-Aliasing
- Fully Software-Compatible with ARM9
- Commercial and Extended Temperature Grades
- ARM Cortex-A8 Core
- ARMv7 Architecture
- TrustZone
- Thumb-2
- MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating-Point SIMD
- Jazelle RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Noninvasive Debug
- ARM Cortex-A8 Memory Architecture:
- 112KB of ROM
- 64KB of Shared SRAM
- Endianess:
- ARM Instructions – Little Endian
- ARM Data – Configurable
- External Memory Interfaces:
- General Purpose Memory Controller (GPMC)
- 16-Bit-Wide Multiplexed Address and Data Bus
- Up to 8 Chip-Select Pins with 128-MB Address Space per Chip-Select Pin
- Glueless Interface to NOR Flash, NAND Flash (with ECC Hamming Code Calculation), SRAM, and Pseudo-SRAM
- Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, and so forth)
- Nonmultiplexed Address and Data Mode (Limited 2-KB Address Space)
- System Direct Memory Access (sDMA) Controller (32 Logical Channels with Configurable Priority)
- Camera Image Signal Processor (ISP)
- CCD and CMOS Imager Interface
- Memory Data Input
- BT.601 (8-Bit) and BT.656 (10-Bit) Digital YCbCr 4:2:2 Interface
- Glueless Interface to Common Video Decoders
- Resize Engine
- Resize Images From 1/4x to 4x
- Separate Horizontal and Vertical Control
- Display Subsystem
- Parallel Digital Output
- Up to 24-Bit RGB
- HD Maximum Resolution
- Supports Up to 2 LCD Panels
- Support for Remote Frame Buffer Interface (RFBI) LCD Panels
- 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
- Composite NTSC and PAL Video
- Luma and Chroma Separate Video (S-Video)
- Rotation 90-, 180-, and 270-Degrees
- Resize Images From 1/4x to 8x
- Color Space Converter
- 8-Bit Alpha Blending
- Serial Communication
- 5 Multichannel Buffered Serial Ports (McBSPs)
- 512-Byte Transmit and Receive Buffer (McBSP1, McBSP3, McBSP4, and McBSP5)
- 5-KB Transmit and Receive Buffer (McBSP2)
- SIDETONE Core Support (McBSP2 and McBSP3 Only) For Filter, Gain, and Mix Operations
- Direct Interface to I2S and PCM Device and TDM Buses
- 128-Channel Transmit and Receive Mode
- Four Master or Slave Multichannel Serial Port Interface (McSPI) Ports
- High-, Full-, and Low-Speed USB OTG Subsystem (12- and 8-Pin ULPI Interface)
- High-, Full-, and Low-Speed Multiport USB Host Subsystem
- 12- and 8-Pin ULPI Interface or 6-, 4-, and 3-Pin Serial Interface
- One HDQ/1-Wire Interface
- UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
- Three Master and Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
- Removable Media Interfaces:
- Three Multimedia Card (MMC)/Secure Digital (SD) with Secure Data I/O (SDIO)
- Comprehensive Power, Reset, and Clock Management
- SmartReflex Technology
- Dynamic Voltage and Frequency Scaling (DVFS)
- Test Interfaces
- IEEE 1149.1 (JTAG) Boundary-Scan Compatible
- ETM Interface
- Serial Data Transport Interface (SDTI)
- 12 32-Bit General-Purpose Timers
- 2 32-Bit Watchdog Timers
- 1 32-Bit 32-kHz Sync Timer
- Up to General-Purpose I/O (GPIO) Pins (Multiplexed with Other Device Functions)
- Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
- Discrete Memory Interface
- Packages:
- 1.8-V I/O and 3.0-V (MMC1 Only),
Specifications
Series | OMAP-35xx | Package | Tray |
Product Status | Obsolete | Core Processor | ARM® Cortex®-A8 |
Number of Cores/Bus Width | 1 Core, 32-Bit | Speed | 600MHz |
Co-Processors/DSP | Multimedia; NEON™ SIMD | RAM Controllers | LPDDR |
Graphics Acceleration | No | Display & Interface Controllers | LCD |
Ethernet | - | SATA | - |
USB | USB 1.x (3), USB 2.0 (1) | Voltage - I/O | 1.8V, 3.0V |
Operating Temperature | 0°C ~ 90°C (TJ) | Security Features | - |
Mounting Type | Surface Mount | Supplier Device Package | 515-POP-FCBGA (14x14) |
Additional Interfaces | HDQ/1-Wire, I²C, McBSP, McSPI, MMC/SD/SDIO, UART | Base Product Number | OMAP3 |
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Availability: 6161 PCS
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