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LMX2595RHAR

RF IC Synthesizer General Purpose 10MHz ~ 20GHz 40-VQFN (6x6)

Manufacturer:

TI
Mfr.Part #:

LMX2595RHAR
Datasheet:

LMX2595RHAR Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

EAR99
EDA/CAD Models:

Request Free CAD Models for LMX2595RHAR

Email: [email protected]

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Tel: +852 95804164

LMX2595RHAR General Description

The LMX2595 high-performance, wideband synthesizer that can generate any frequency from 10 MHz to 20 GHz. An integrated doubler is used for frequencies above 15 GHz. The high-performance PLL with figure of merit of –236 dBc/Hz and high-phase detector frequency can attain very low in-band noise and integrated jitter. The high-speed N-divider has no pre-divider, thus significantly reducing the amplitude and number of spurs. There is also a programmable input multiplier to mitigate integer boundary spurs.

The LMX2595 allows users to synchronize the output of multiple devices and also enables applications that need deterministic delay between input and output. A frequency ramp generator can synthesize up to two segments of ramp in an automatic ramp generation option or a manual option for maximum flexibility. The fast calibration algorithm allows changing frequencies faster than 20 µs. The LMX2595 adds support for generating or repeating SYSREF (compliant to JESD204B standard) designed for low-noise clock sources in high-speed data converters. A fine delay adjustment (9-ps resolution) is provided in this configuration to account for delay differences of board traces.

The output drivers within LMX2595 deliver output power as high as 7 dBm at 15-GHz carrier frequency. The device runs from a single 3.3-V supply and has integrated LDOs that eliminate the need for on-board low noise LDOs.

Key Features

10-MHz to 20-GHz output frequency
–110 dBc/Hz phase noise at 100-kHz offset with 15-GHz carrier
45-fs rms jitter at 7.5 GHz (100 Hz to 100 MHz)
Programmable output power
PLL key specifications
- Figure of merit: –236 dBc/Hz
- Normalized 1/f noise: –129 dBc/Hz
- High phase detector frequency
  - 400-MHz integer mode
  - 300-MHz fractional mode
- 32-bit fractional-N divider
Remove integer boundary spurs with programmable input multiplier
Synchronization of output phase across multiple devices
Support for SYSREF with 9-ps resolution programmable delay
Frequency ramp and chirp generation ability for FMCW applications
< 20-µs VCO calibration speed
3.3-V single power supply operation

Specifications

Source Content uid	LMX2595RHAR	Pbfree Code	Yes
Part Life Cycle Code	Active	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.39.00.01
Date Of Intro	2017-06-30	Analog IC - Other Type	PHASE LOCKED LOOP
JESD-30 Code	S-PQCC-N40	Moisture Sensitivity Level	3
Number of Functions	1	Number of Terminals	40
Peak Reflow Temperature (Cel)	260	Surface Mount	YES
Temperature Grade	INDUSTRIAL	Terminal Finish	NICKEL PALLADIUM GOLD SILVER
Terminal Form	NO LEAD	Terminal Position	QUAD
Time@Peak Reflow Temperature-Max (s)	30