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See Technical Specifications

K4B2G0846D-HCK0

DDR DRAM, 256MX8, 0.225ns, CMOS, PBGA78

Manufacturer:

SAMSUNG SEMICONDUCTOR INC
Mfr.Part #:

K4B2G0846D-HCK0
Datasheet:

K4B2G0846D-HCK0 Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
ECCN Code:

EAR99
HTS Code:

8542.32.00.36
EDA/CAD Models:

Request Free CAD Models for K4B2G0846D-HCK0

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Key Features

The 2Gb DDR3 SDRAM D-die is organized as a 64Mbit x 4 I/Os x 8banks, 32Mbit x 8 I/Os x 8banks device. This synchronous device achieves high speed double-data-rate transfer rates of up to 1600Mb/sec/pin (DDR3-1600) for general applications. The chip is designed to comply with the following key DDR3 SDRAM features such as posted CAS, Programmable CWL, Internal (Self) Calibration, On Die Termination using ODT pin and Asynchronous Reset .

Specifications

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
ECCN Code	EAR99	HTS Code	8542.32.00.36
Access Mode	MULTI BANK PAGE BURST	Access Time-Max	0.225 ns
Additional Feature	AUTO/SELF REFRESH	Clock Frequency-Max (fCLK)	800 MHz
I/O Type	COMMON	Interleaved Burst Length	8
JESD-30 Code	R-PBGA-B78	Length	11 mm
Memory Density	2147483648 bit	Memory IC Type	DDR3 DRAM
Memory Width	8	Number of Functions	1
Number of Ports	1	Number of Terminals	78
Number of Words	268435456 words	Number of Words Code	256000000
Operating Mode	SYNCHRONOUS	Operating Temperature-Max	85 °C
Operating Temperature-Min		Organization	256MX8
Output Characteristics	3-STATE	Power Supplies	1.5 V
Qualification Status	Not Qualified	Refresh Cycles	8192
Seated Height-Max	1.2 mm	Self Refresh	YES
Sequential Burst Length	8	Standby Current-Max	0.012 A
Supply Current-Max	0.14 mA	Supply Voltage-Max (Vsup)	1.575 V
Supply Voltage-Min (Vsup)	1.425 V	Supply Voltage-Nom (Vsup)	1.5 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	OTHER	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Width	7.5 mm