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F28M36P63C2ZWTT +BOM

C28x/ARM® Cortex®-M3 C2000™ C28x + ARM® Cortex® M3 Concerto™ Microcontroller IC 32-Bit Dual-Core 125MHz/150MHz 512KB/1MB FLASH 289-NFBGA (16x16)

Manufacturer:

TI
Mfr.Part #:

F28M36P63C2ZWTT
Datasheet:

F28M36P63C2ZWTT Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Reach Compliance Code:

compliant
ECCN Code:

3A991.A.2
EDA/CAD Models:

Request Free CAD Models for F28M36P63C2ZWTT

Email: [email protected]

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F28M36P63C2ZWTT General Description

The Concerto family is a multicore system-on-chip microcontroller unit (MCU) with independent communication and real-time control subsystems. The F28M36x family of devices is the second series in the Concerto family.

The communications subsystem is based on the industry-standard 32-bit Arm Cortex-M3 CPU and features a wide variety of communication peripherals, including Ethernet 1588, USB OTG with PHY, Controller Area Network (CAN), UART, SSI, I2C, and an external interface.

The real-time control subsystem is based on TI’s industry-leading proprietary 32-bit C28x floating-point CPU and features the most flexible and high-precision control peripherals, including ePWMs with fault protection, and encoders and captures—all as implemented by TI’s TMS320C2000™ Entry performance MCUs and Premium performance MCUs. In addition, the C28-CPU has been enhanced with the addition of the VCU instruction accelerator that implements efficient Viterbi, Complex Arithmetic, 16-bit FFTs, and CRC algorithms.

A high-speed analog subsystem and supplementary RAM memory is shared, along with on-chip voltage regulation and redundant clocking circuitry. Safety considerations also include Error Correction Code (ECC), parity, and code secure memory, as well as documentation to assist with system-level industrial safety certification.

Key Features

Master Subsystem — Arm^® Cortex^®-M3
- 125 MHz
- Embedded memory
  - Up to 1MB of flash (ECC)
  - Up to 128KB of RAM (ECC or parity)
  - Up to 64KB of shared RAM
  - 2KB of IPC Message RAM
- Five Universal Asynchronous Receiver/Transmitters (UARTs)
- Four Synchronous Serial Interfaces (SSIs)
  and a Serial Peripheral Interface (SPI)
- Two Inter-integrated Circuits (I2Cs)
- Universal Serial Bus On-the-Go (USB-OTG) + PHY
- 10/100 ENET 1588 MII
- Two Controller Area Network, D_CAN, modules (pin-bootable)
- 32-channel Micro Direct Memory Access (µDMA)
- Dual security zones (128-bit password per zone)
- External Peripheral Interface (EPI)
- Micro Cyclic Redundancy Check (µCRC) module
- Four general-purpose timers
- Two watchdog timer modules
- Three external interrupts
- Endianness: little endian
Clocking
- On-chip crystal oscillator and external clock input
- Dynamic Phase-Locked Loop (PLL) ratio changes supported
1.2-V digital, 1.8-V analog, 3.3-V I/O design
Interprocessor Communications (IPC)
- 32 handshaking channels
- Four channels generate IPC interrupts
- Can be used to coordinate transfer of data through IPC Message RAMs
Up to 142 individually programmable, multiplexed General-Purpose Input/Output (GPIO) pins
- Glitch-free I/Os
Control Subsystem — TMS320C28x 32-bit CPU
- 150 MHz
- C28x core hardware built-in self-test
- Embedded memory
  - Up to 512KB of flash (ECC)
  - Up to 36KB of RAM (ECC or parity)
  - Up to 64KB of shared RAM
  - 2KB of IPC Message RAM
- IEEE-754 single-precision Floating-Point Unit (FPU)
- Viterbi, Complex Math, CRC Unit (VCU)
- Serial Communications Interface (SCI)
- SPI
- I2C
- 6-channel Direct Memory Access (DMA)
- 12 Enhanced Pulse Width Modulator (ePWM) modules
  - 24 outputs (16 high-resolution)
- Six 32-bit Enhanced Capture (eCAP) modules
- Three 32-bit Enhanced Quadrature Encoder Pulse (eQEP) modules
- Multichannel Buffered Serial Port (McBSP)
- EPI
- One security zone (128-bit password)
- Three 32-bit timers
- Endianness: little endian
Analog Subsystem
- Dual 12-bit Analog-to-Digital Converters (ADCs)
- Up to 2.88 MSPS
- Up to 24 channels
- Four Sample-and-Hold (S/H) circuits
- Up to six comparators with 10-bit Digital-to-Analog Converter (DAC)
Package
- 289-ball ZWT New Fine Pitch Ball Grid Array (nFBGA)
Temperature options:
- T: –40ºC to 105ºC Junction
- S: –40ºC to 125ºC Junction

Specifications

Source Content uid	F28M36P63C2ZWTT	Pbfree Code	Yes
Part Life Cycle Code	Active	Reach Compliance Code	compliant
ECCN Code	3A991.A.2	HTS Code	8542.31.00.01
Has ADC	YES	Address Bus Width	28
Bit Size	32	Boundary Scan	YES
CPU Family	CORTEX-M3	DAC Channels	NO
DMA Channels	YES	External Data Bus Width	32
Format	FLOATING POINT	Integrated Cache	NO
JESD-30 Code	S-PBGA-B289	Low Power Mode	YES
Moisture Sensitivity Level	3	Number of DMA Channels	32
Number of External Interrupts	3	Number of I/O Lines	142
Number of Serial I/Os	7	Number of Terminals	289
Number of Timers	4	On Chip Data RAM Width	8
PWM Channels	YES	Peak Reflow Temperature (Cel)	260
RAM (words)	232	Surface Mount	YES
Technology	CMOS	Temperature Grade	INDUSTRIAL
Terminal Finish	TIN SILVER COPPER	Terminal Form	BALL
Terminal Position	BOTTOM	Time@Peak Reflow Temperature-Max (s)	30
uPs/uCs/Peripheral ICs Type	MICROCONTROLLER, RISC