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See Technical Specifications

EP4CE30F23C8N

2016 RoHS Compliant BALL Not Qualified FPGA 0C~85C TJ 472.5MHz 1.21.2/3.32.5V 2.4mm

Manufacturer:

Intel
Mfr.Part #:

EP4CE30F23C8N
Datasheet:

EP4CE30F23C8N Datasheet (PDF)
Programmabe:

Not Verified
Number of LABs/CLBs:

1803
Number of Logic Elements/Cells:

28848
Total RAM Bits:

608256
EDA/CAD Models:

Request Free CAD Models for EP4CE30F23C8N

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EP4CE30F23C8N General Description

FPGA, CYCLONE IV, 30K, 484FBGA; No. of Logic Blocks: 1803; No. of Macrocells: 28848; FPGA Family: Cyclone IV; Logic Case Style: FBGA; No. of Pins: 484Pins; No. of Speed Grades: 8; Total RAM Bits: 594Kbit; No. of I/O's: 328I/O's; Clock Management: PLL; Core Supply Voltage Min: 1.15V; Core Supply Voltage Max: 1.25V; I/O Supply Voltage: 3.3V; Operating Frequency Max: 472.5MHz; Product Range: -; MSL: MSL 3 - 168 hours; SVHC: No SVHC (17-Dec-2015); Core Supply Voltage Range: 1.15V to 1.25V; Logic Function Number: FPGA; Operating Temperature Max: 85°C; Operating Temperature Min: 0°C; Operating Temperature Range: 0°C to +85°C

Key Features

The Cyclone IV device family offers the following features:

Low-cost, low-power FPGA fabric:

6K to 150K logic elements

Up to 6.3 Mb of embedded memory

Up to 360 1818 multipliers for DSP processing intensive applications

Protocol bridging applications for under 1.5 W total power

Cyclone IV GX devices offer up to eight high-speed transceivers that provide:

Data rates up to 3.125 Gbps

8B/10B encoder/decoder

8-bit or 10-bit physical media attachment (PMA) to physical coding sublayer (PCS) interface

Byte serializer/deserializer (SERDES)

Word aligner

Rate matching FIFO

TX bit slipper for Common Public Radio Interface (CPRI)

Electrical idle

Dynamic channel reconfiguration allowing you to change data rates andprotocols on-the-fly

Static equalization and pre-emphasis for superior signal integrity

150 mW per channel power consumption

Flexible clocking structure to support multiple protocols in a single transceiver block

Cyclone IV GX devices offer dedicated hard IP for PCI Express (PIPE) (PCIe) Gen 1:

1, 2, and 4 lane configurations

End-point and root-port configurations

Up to 256-byte payload

One virtual channel

2 KB retry buffer

4 KB receiver (Rx) buffer

Cyclone IV GX devices offer a wide range of protocol support:

PCIe (PIPE) Gen 1 1, 2, and 4 (2.5 Gbps)

Gigabit Ethernet (1.25 Gbps)

CPRI (up to 3.072 Gbps)

XAUI (3.125 Gbps)

Triple rate serial digital interface (SDI) (up to 2.97 Gbps)

Serial RapidIO (3.125 Gbps)

Basic mode (up to 3.125 Gbps)

V-by-One (up to 3.0 Gbps)

DisplayPort (2.7 Gbps)

Serial Advanced Technology Attachment (SATA) (up to 3.0 Gbps)

OBSAI (up to 3.072 Gbps)

Up to 532 user I/Os

LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx

Support for DDR2 SDRAM interfaces up to 200 MHz

Support for QDRII SRAM and DDR SDRAM up to 167 MHz

Up to eight phase-locked loops (PLLs) per device

Offered in commercial and industrial temperature grades

Application

Altera’s new Cyclone® IV FPGA device family extends the Cyclone FPGA series leadership in providing the market’s lowest-cost, lowest-power FPGAs, now with a transceiver variant. Cyclone IV devices are targeted to high-volume, cost-sensitive applications, enabling system designers to meet increasing bandwidth requirements while lowering costs.

Specifications

Programmabe	Not Verified	Number of LABs/CLBs	1803
Number of Logic Elements/Cells	28848	Total RAM Bits	608256
Number of I/O	328	Number of Gates	-
Voltage - Supply	1.15V ~ 1.25V	Mounting Type	Surface Mount
Operating Temperature	0°C ~ 85°C (TJ)