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See Technical Specifications

EP2S130F1020C5N +BOM

Stratix® II Field Programmable Gate Array (FPGA) IC 742 6747840 132540 1020-BBGA

Manufacturer:

Intel
Mfr.Part #:

EP2S130F1020C5N
Datasheet:

EP2S130F1020C5N Datasheet (PDF)
Part Life Cycle Code:

Obsolete
Reach Compliance Code:

compliant
HTS Code:

8542.39.00.01
Clock Frequency-Max:

640 MHz
EDA/CAD Models:

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EP2S130F1020C5N General Description

Stratix® II Field Programmable Gate Array (FPGA) IC 742 6747840 132540 1020-BBGA

Key Features

The Stratix II family offers the following
features:
15,600 to 179,400 equivalent LEs; see Table 1–1 New and innovative adaptive logic module (ALM), the basic building block of the Stratix II architecture, maximizes performance and resource usage efficiency Up to 9,383,040 RAM bits (1,172,880 bytes) available without reducing logic resources TriMatrix memory consisting of three RAM block sizes to implement true dual-port memory and first-in first-out (FIFO) buffers High-speed DSP blocks provide dedicated implementation of multipliers (at up to 450 MHz), multiply-accumulate functions, and finite impulse response (FIR) filters Up to 16 global clocks with 24 clocking resources per device region Clock control blocks support dynamic clock network enable/disable, which allows clock networks to power down to reduce power consumption in user mode Up to 12 PLLs (four enhanced PLLs and eight fast PLLs) per device provide spread spectrum, programmable bandwidth, clock switchover, real-time PLL reconfiguration, and advanced multiplication and phase shifting Support for numerous single-ended and differential I/O standards High-speed differential I/O support with DPA circuitry for 1-Gbps performance Support for high-speed networking and communications bus standards including Parallel RapidIO, SPI-4 Phase 2 (POS-PHY Level 4), HyperTransport™ technology, and SFI-4 Support for high-speed external memory, including DDR and DDR2 SDRAM, RLDRAM II, QDR II SRAM, and SDR SDRAM Support for multiple intellectual property megafunctions from Altera MegaCore® functions and Altera Megafunction Partners Program (AMPPSM) megafunctions Support for design security using configuration bitstream encryption Support for remote configuration updates

Specifications

Part Life Cycle Code	Obsolete	Reach Compliance Code	compliant
HTS Code	8542.39.00.01	Clock Frequency-Max	640 MHz
Combinatorial Delay of a CLB-Max	5.962 ns	JESD-30 Code	S-PBGA-B1020
JESD-609 Code	e1	Length	33 mm
Moisture Sensitivity Level	3	Number of CLBs	53016
Number of Inputs	742	Number of Logic Cells	132540
Number of Outputs	734	Number of Terminals	1020
Operating Temperature-Max	85 °C	Operating Temperature-Min
Organization	53016 CLBS	Programmable Logic Type	FIELD PROGRAMMABLE GATE ARRAY
Qualification Status	Not Qualified	Seated Height-Max	3.5 mm
Supply Voltage-Max	1.25 V	Supply Voltage-Min	1.15 V
Supply Voltage-Nom	1.2 V	Surface Mount	YES
Technology	CMOS	Temperature Grade	OTHER
Terminal Finish	TIN SILVER COPPER	Terminal Form	BALL
Terminal Pitch	1 mm	Terminal Position	BOTTOM
Width	33 mm