This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

CDCLVD1208RHDR

Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer

Manufacturer:

TI
Mfr.Part #:

CDCLVD1208RHDR
Datasheet:

CDCLVD1208RHDR Datasheet (PDF)
Pbfree Code:

Yes
Part Life Cycle Code:

Active
Pin Count:

28
Reach Compliance Code:

compliant
EDA/CAD Models:

Request Free CAD Models for CDCLVD1208RHDR

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

CDCLVD1208RHDR General Description

The CDCLVD1208 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 8 pairs of differential LVDS clock outputs (OUT0 through OUT7) with minimum skew for clock distribution. The CDCLVD1208 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1208 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single-ended mode, the appropriate bias voltage, V_{AC_REF}, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail-safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1208 is packaged in small, 28-pin, 5-mm × 5-mm VQFN package.

Key Features

2:8 Differential Buffer
Low Additive Jitter: < 300-fs RMS in 10-kHz to 20-MHz
Low Output Skew of 45 ps (Maximum)
Universal Inputs Accept LVDS, LVPECL, and LVCMOS
Selectable Clock Inputs Through Control Pin
8 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency: Up to 800 MHz
Device Power Supply: 2.375 V to 2.625 V
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 5-mm × 5-mm, 28-Pin VQFN (RHD)
ESD Protection Exceeds 3-kV HBM, 1-kV CDM
APPLICATIONS
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General-Purpose Clocking

All other trademarks are the property of their respective owners

Specifications

Source Content uid	CDCLVD1208RHDR	Pbfree Code	Yes
Part Life Cycle Code	Active	Pin Count	28
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.39.00.01	Family	CDC
Input Conditioning	DIFFERENTIAL MUX	JESD-30 Code	S-PQCC-N28
Logic IC Type	LOW SKEW CLOCK DRIVER	Moisture Sensitivity Level	2
Number of Functions	1	Number of Inverted Outputs
Number of Terminals	28	Number of True Outputs	8
Packing Method	TR	Peak Reflow Temperature (Cel)	260
Surface Mount	YES	Temperature Grade	INDUSTRIAL
Terminal Finish	Nickel/Palladium/Gold (Ni/Pd/Au)	Terminal Form	NO LEAD
Terminal Position	QUAD	Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED