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CAXC4T245QWBQBRQ1

Automotive 4-bit dual-supply bus transceiver w/ configurable voltage translation, 3-state output

Manufacturer:

Texas Instruments, Inc
Mfr.Part #:

CAXC4T245QWBQBRQ1
Datasheet:

CAXC4T245QWBQBRQ1 Datasheet (PDF)
Technology family:

AXC
Applications:

JTAG, SPI, UART
Bits (#):

2, 4
High input voltage (min) (V):

0.45, 0.455
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CAXC4T245QWBQBRQ1 General Description

The SN74AXC4T245-Q1 AEC-Q100 qualified device is a four-bit non-inverting bus transceiver that uses two individually configurable power-supply rails. The device is operational with both V_CCA and V_CCB supplies as low as 0.65 V. The A port is designed to track V_CCA, which accepts any supply voltage from 0.65 V to 3.6 V. The B port is designed to track V_CCB, which also accepts any supply voltage from 0.65 V to 3.6 V. Additionally the SN74AXC4T245-Q1 is compatible with a single-supply system.

The SN74AXC4T245-Q1 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level of the direction-control inputs (1DIR and 2DIR). The output-enable inputs (1 OE and 2 OE) are used to disable the outputs so the buses are effectively isolated. The SN74AXC4T245-Q1 device is designed so the control pins (xDIR and x OE) are referenced to V_CCA.

To ensure the high-impedance state of the level shifter I/Os during power up or power down, the x OE pins should be tied to V_CCA through a pull-up resistor.

This device is fully specified for partial-power-down applications using the I_off current. The I_off protection circuitry ensures that no excessive current is drawn from or to an input, output, or combined I/O that is biased to a specific voltage while the device is powered down.

The V_CC isolation feature ensures that if either V_CCA or V_CCB is less than 100 mV, both I/O ports enter a high-impedance state by disabling their outputs.

Glitch-Free power supply sequencing allows either supply rail to be powered on or off in any order while providing robust power sequencing performance.

Key Features

AEC-Q100 qualified for automotive applications
Available in wettable flank QFN (WBQB) package
Fully-configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
Operating temperature from –40°C to +125°C
Multiple direction control pins to allow simultaneous up and down translation
Glitch-free power supply sequencing
Up to 380 Mbps support when translating from 1.8 V to 3.3 V
V_CC isolation feature:
- If either V_CC input is below 100 mV, all I/O outputs are disabled and become high impedance
I_off supports partial-power-down mode operation
Compatible with AVC-family level shifters
Latch-up performance exceeds 100 mA per JESD 78, class II
ESD protection exceeds JEDEC JS-001
- 8000-V human-body model
- 1000-V charged-device model

Specifications

Technology family	AXC	Applications	JTAG, SPI, UART
Bits (#)	2, 4	High input voltage (min) (V)	0.45, 0.455
High input voltage (max) (V)	3.6	Vout (min) (V)	0.65
Vout (max) (V)	3.6	Data rate (max) (MBps)	380
IOH (max) (mA)	-12	IOL (max) (mA)	12
Supply current (max) (µA)	23, 40	Features	Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc isolation
Input type	CMOS, Standard CMOS	Output type	3-State, Balanced CMOS, Push-Pull
Rating	Automotive	Operating temperature range (°C)	-40 to 125
feature-logic-family		feature-logic-function
feature-translation		feature-process-technology
feature-output-type		feature-maximum-low-level-output-current-ma
feature-maximum-high-level-output-current-ma		feature-minimum-operating-supply-voltage-v
feature-maximum-operating-supply-voltage-v		feature-packaging
feature-rad-hard		feature-pin-count
feature-cecc-qualified		feature-esd-protection
feature-military		feature-aec-qualified	Yes
feature-aec-qualified-number	AEC-Q100	feature-auto-motive	Yes
feature-p-pap	Yes	feature-eccn-code	EAR99
feature-svhc		feature-svhc-exceeds-threshold