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MC68LC060RC50

68060 Microprocessor IC M680x0 1 Core, 32-Bit 50MHz 206-PGA (47.25x47.25)

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68060 Microprocessor IC M680x0 1 Core, 32-Bit 50MHz 206-PGA (47.25x47.25)

The main features of the MC68060 are as follows:
1.6–1.7 Times the MC68040 Performance at the Same Clock Rate with Existing Compliers. 3.2–3.4 Times the Performance of a 25 MHZ MC68040.
Harvard Architecture with Independent, Decoupled Fetch and Execution Pipelines.
Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped Branch Cache for Improved Branch Instruction Performance.
A Superscalar Pipeline and Dual Integer Execution Units Achieving Simultaneous, but not Out-of-Order Instruction Execution.
An IEEE Standard, MC68040- and MC68881-/MC68882-Compatible FPU.
An MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry Address Translation Caches
Dual 8-Kbyte Caches (Instruction Cache and Data Cache)
A Flexible, High-Bandwidth Synchronous Bus Interface
User Object-Code Compatible with All Earlier M68000 Microprocessors

Part Life Cycle Code	Active	Pin Count	206
Reach Compliance Code		Additional Feature	BUS CONTROLLER
Address Bus Width	32	Bit Size	32
Boundary Scan	YES	Clock Frequency-Max	50 MHz
External Data Bus Width	32	Format	FIXED POINT
Integrated Cache	YES	JESD-30 Code	S-CPGA-P206
Length	47.245 mm	Low Power Mode	YES
Moisture Sensitivity Level	NOT SPECIFIED	Number of Terminals	206
Peak Reflow Temperature (Cel)	NOT SPECIFIED	Qualification Status	COMMERCIAL
Seated Height-Max	3.05 mm	Speed	50 MHz
Supply Voltage-Max	3.465 V	Supply Voltage-Min	3.135 V
Supply Voltage-Nom	3.3 V	Surface Mount	NO
Technology	CMOS	Terminal Finish	NOT SPECIFIED
Terminal Form	PIN/PEG	Terminal Pitch	2.54 mm
Terminal Position	PERPENDICULAR	Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED
Width	47.245 mm	uPs/uCs/Peripheral ICs Type	MICROPROCESSOR