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See Technical Specifications

HMC7044LP10BE

High Performance, 3.2 GHz, 14-Output Jitter Attenuator with JESD204B

Manufacturer:

Analog Devices, Inc
Mfr.Part #:

HMC7044LP10BE
Datasheet:

HMC7044LP10BE Datasheet (PDF)
packingQty:

Cut Tape,500
packingOption:

Cut Tape
tempRange:

-40 to 85C
EDA/CAD Models:

Request Free CAD Models for HMC7044LP10BE

Email: [email protected]

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Tel: +852 95804164

HMC7044LP10BE General Description

The HMC7044 is a high performance, dual-loop, integer-N jitter attenuator capable of performing reference selection and generation of ultralow phase noise frequencies for high speed data converters with either parallel or serial (JESD204B type) interfaces. The HMC7044 features two integer mode PLLs and overlapping on-chip VCOs that are SPI-selectable with wide tuning ranges around 2.5 GHz and 3 GHz, respectively. The device is designed to meet the requirements of GSM and LTE base station designs, and offers a wide range of clock management and distribution features to simplify baseband and radio card clock tree designs. The HMC7044 provides 14 low noise and configurable outputs to offer flexibility in interfacing with many different components including data converters, field-programmable gate arrays (FPGAs), and mixer local oscillators (LOs).

Key Features

Ultralow rms jitter: 44 fs typical (12 kHz to 20 MHz) at 2457.6 MHz
Noise floor: −156 dBc/Hz at 2457.6 MHz
Low phase noise: −141.7 dBc/Hz at 800 kHz, 983.04 MHz output
Up to 14 LVDS, LVPECL, or CML type device clocks (DCLKs) from PLL2

Maximum CLKOUTx/CLKOUTx and SCLKOUTx/SCLKOUTx frequency up to 3200 MHz

JESD204B-compatible system reference (SYSREF) pulses
25 ps analog, and ½ VCO cycle digital delay independently programmable on each of 14 clock output channels
SPI-programmable phase noise vs. power consumption