This website uses cookies. By using this site, you consent to the use of cookies. For more information, please take a look at our Privacy Policy.

Images are for reference only,

See Technical Specifications

MC10EP139DTG

3.3 V / 5.0 V ECL ÷·2/4, ÷·4/5/6 Divider

Manufacturer:

ON Semiconductor, LLC
Mfr.Part #:

MC10EP139DTG
Datasheet:

MC10EP139DTG Datasheet (PDF)
Case Outline:

9.48
MSL Temp (°C):

260
Container Type:

TUBE
Series:

MC10EP139
EDA/CAD Models:

Request Free CAD Models for MC10EP139DTG

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

MC10EP139DTG General Description

The MC10/100EP139 is a low skew divide by 2/4, divide by 4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, LVPECL input signals. In addition, by using the V_BB output, a sinusoidal source can be AC coupled into the device. If a single-ended input is to be used, the V_BB output should be connected to the CLKbar input and bypassed to ground via a 0.01uF capacitor.

The common enable (ENbar) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. The internal enable flip-flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip-flops will attain a random state; therefore, for systems which utilize multiple EP139s, the master reset (MR) input must be asserted to ensure synchronization. For systems which only use one EP139, the MR pin need not be exercised as the internal divider design ensures synchronization between the divide by 2/4 and the divide by 4/5/6 outputs of a single device. All V_CC and V_EE pins must be externally connected to power supply to guarantee proper operation.

The 100 Series contains temperature compensation.

Key Features

Maximum Frequency >1.0 GHz Typical
50ps Output-to-Output Skew
PECL Mode Operating Range: V_CC=3.0 V to 5.5 V with V_EE = 0 V
NECL Mode Operating Range: V_CC = 0 V with V_EE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Synchronous Enable/Disable
Master Reset for Synchronization of Multiple Chips
V_BB Output
Pb-Free Packages are Available

Application

Low-Clock Skew Generation

Specifications

Status	Active	Case Outline	9.48
MSL Temp (°C)	260	Container Type	TUBE
Product Category	Clock Generators & Support Products	Series	MC10EP139
Type	Clock Generators	Maximum Input Frequency	-
Max Output Freq	1 GHz	Number of Outputs	4 Output
Duty Cycle - Max	50 %	Operating Supply Voltage	3 V to 5.5 V
Operating Supply Current	84 mA	Minimum Operating Temperature	- 40 C
Maximum Operating Temperature	+ 85 C	Mounting Style	SMD/SMT
Product Type	Clock Generators	Factory Pack Quantity	75
Subcategory	Clock & Timer ICs	Unit Weight	0.006737 oz