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EPM7512AEFC256-7

CPLD MAX 7000A Family 10K Gates 512 Macro Cells 116.3MHz 3.3V 256-Pin FBGA

Email: [email protected]

Skype: live:.cid.ab6b29428937b76

Tel: +852 95804164

The features of EPM7512AEFC256-7 include a 256-pin BGA package with a pin-out diagram
It has predictable internal delays for determining worst-case timing

The applications of EPM7512AEFC256-7 are not explicitly mentioned in the provided search results

Part Life Cycle Code	Obsolete	Reach Compliance Code	not_compliant
ECCN Code	3A991.D	HTS Code	8542.39.00.01
Additional Feature	512 MACROCELLS; 32 LABS; CONFIGURABLE I/O OPERATION WITH 2.5 OR 3.3	Clock Frequency-Max	116.3 MHz
In-System Programmable	YES	JESD-30 Code	S-PBGA-B256
JESD-609 Code	e0	JTAG BST	YES
Length	17 mm	Moisture Sensitivity Level	3
Number of Dedicated Inputs		Number of I/O Lines	212
Number of Macro Cells	512	Number of Terminals	256
Operating Temperature-Max	70 °C	Operating Temperature-Min
Organization	0 DEDICATED INPUTS, 212 I/O	Output Function	MACROCELL
Peak Reflow Temperature (Cel)	220	Programmable Logic Type	EE PLD
Propagation Delay	7.5 ns	Qualification Status	Not Qualified
Seated Height-Max	2.1 mm	Supply Voltage-Max	3.6 V
Supply Voltage-Min	3 V	Supply Voltage-Nom	3.3 V
Surface Mount	YES	Technology	CMOS
Temperature Grade	COMMERCIAL	Terminal Finish	Tin/Lead (Sn63Pb37)
Terminal Form	BALL	Terminal Pitch	1 mm
Terminal Position	BOTTOM	Time@Peak Reflow Temperature-Max (s)	20
Width	17 mm